Digital integrated circuits: FPGA and ASIC. VHDL syntax. Functional description, implementation and verification of a logic project. Synchronous and asynchronous logic machines, problems related to signal timing. Logic errors and their treatment. Practical implementation of logic circuit examples on PCB with FPGA, with increasing complexity: from VHDL coding to laboratory test of the correct functionality. Integration of FPGA with Arduino system.
D. Naylor and S. Jones, “VHDL: a logic synthesis approach”, Chapman & Hall, 1997
Z. Navabi, “VHDL. Analysis and modeling of digital systems”, McGraw-Hill, 1993
S. Rajan, “Essential VHDL: RTL synthesis done right”, CL Books, 1997
Learning Objectives
Knowledge and understanding of: integrated digital circuits (FPGA and ASIC), their formal description in VHDL language, proper project coding and verification methodologies, cases of logic errors and their treatment.
Ability to apply knowledge and understanding for: implementation of typical examples of digital circuits of various complexity on FPGA, from the VHDL coding phase to the simulation phase and finally to the laboratory test of the configured FPGA device; implementation of digital interfaces with Arduino system.
Judgement making: choices of optimizations of the formal description of a digital circuit, of minimization of potential logic errors, of appropriate control of circuit timing and amount of data managed.
Prerequisites
Elements of analog electronics, including: electrical circuits, structor of semiconductors and main transistor types. Elementary logics and boolean algebra. Elements of digital electronics: basic logic gates and their combinations, memory elements (flip-flop). Use of text and window PC applications and of basic instrumentation of electronics laboratory (oscilloscope, soldering station).
Teaching Methods
Lesson with screen presentation, written notes, laboratory activity with practical exercises, circuit implementation and test.
Type of Assessment
Oral examination. Discussion of one of the logic projects implemented by the student in laboratory, description of the features of the logic structure, of the missing optimizations in view of the intended application, of the problems found and how they could be solved. Generalization from the specific case found to the general one.
Evaluation criteria: ability to organize the knowledge; ability to critically and analitically discuss on the implemented project; competence in using the technical terms involved; ability of abstraction from the specific case to the general case.
Course program
Lesson. Outline of the structure of digital integrated circuits (FPGA and ASIC). Introduction to HDL languages. Basic elements of VHDL syntax. Functional description of logic circuits. Hierarchic block design.
Lesson. Analysis of compilation and verification phases of an HDL project: synthesis of the logic circuit, device configuration, functional and time simulation, laboratory tests. Examples of advanced VHDL design.
Lesson. Concept of synchronous and asynchronous logic machine. Time behaviour of circuit signals and relation with setup/hold time. VHDL description of synchronous machine. Examples of VHDL-coded projects. Presentation of the main application cases.
Lesson. Upset and logic error in a synchronous circuit. Upset in asynchronous circuit and resynchronization without logic error. Upset from external perturbations, examples of logic redundancy and of methods to detect the logic error.
Laboratory. VHDL design, compilation and simulation of a simple circuit with hierarchic blocks. Implementation of a VHDL synchronous machine and interface with Arduino system, with an FPGA and dedicated PCB. Laboratory tests and measurements to verify the effective functionality.